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| MCP14700 Dual Input Synchronous MOSFET Driver Features * Independent PWM Input Control for High-Side and Low-Side Gate Drive * Input Logic Level Threshold 3.0V TTL Compatible * Dual Output MOSFET Drive for Synchronous Applications * High Peak Output Current: 2A (typical) * Internal Bootstrap Blocking Device * +36V BOOT Pin Maximum Rating * Low Supply Current: 45 A (typical) * High Capacitive Load Drive Capability: - 3300 pF in 10.0 ns (typical) * Input Voltage Undervoltage Lockout Protection * Overtemperature Protection * Space Saving Packages: - 8-Lead SOIC - 8-Lead 3x3 DFN General Description The MCP14700 is a high-speed synchronous MOSFET driver designed to optimally drive a high-side and low-side N-Channel MOSFET. The MCP14700 has two PWM inputs to allow independent control of the external N-Channel MOSFETs. Since there is no internal cross conduction protection circuitry the external MOSFET dead time can be tightly controlled allowing for more efficient systems or unique motor control algorithms. The transition thresholds for the PWM inputs are typically 1.6V on a rising PWM input signal and typically 1.2V on a falling PWM input signal. This makes the MCP14700 ideally suited for controllers that utilize 3.0V TTL/CMOS logic. The PWM inputs are internally pulled low ensuring the output drive signals are low if the inputs are floating. The HIGHDR and LOWDR peak source current capability of the MCP14700 device is typically 2A. While the HIGHDR can sink 2A peak typically, the LOWDR can sink 3.5A peak typically. The low resistance pull-up and pull-down drive allow the MCP14700 to quickly transition a 3300 pF load in typically 10 ns. Bootstrapping for the high-side drive is internally implemented which allows for a reduced system cost and design complexity. The MCP14700 features under voltage lock out (UVLO) with a typical hysteresis of 500 mV. Overtemperature protection with hysteresis is also featured on the device. Applications * 3-Phase BLDC Motor Control * High Efficient Synchronous DC/DC Buck Converters * High Current Low Output Voltage Synchronous DC/DC Buck Converters * High Input Voltage Synchronous DC/DC Buck Converters * Core Voltage Supplies for Microprocessors Package Types MCP14700 SOIC PHASE 1 PWMHI 2 PWMLO 3 GND 4 8 HIGHDR 7 BOOT 6 VCC 5 LOWDR MCP14700 3x3 DFN* PHASE 1 PWMHI 2 PWMLO 3 GND 4 EP 9 8 HIGHDR 7 BOOT 6 VCC 5 LOWDR * Includes Exposed Thermal Pad (EP); see Table 3-1. (c) 2009 Microchip Technology Inc. DS22201A-page 1 MCP14700 Typical Application Schematic Synchronous Buck Application CBOOT VCC = 5.0V BOOT HIGHDR VCC MCP14700 PWMHI PHASE PWMLO LOWDR GND VBUCK = 30V CURRENT SENSE dsPIC33FJ06GS101 PWM1L PWM1H AN0 AN1 CURRENT SENSE 3-Phase BLDC Motor Control Application 24V VCC VCC BOOT HIGHDR 24V BOOT HIGHDR VCC VCC PWM5 PWM6 PWM1 PWM2 MCP14700 PWMHI PHASE PWMLO LOWDR GND MCP14700 PHASE PWMH LOWDR PWMLO GND SENSE NODE 24V VCC PWM3 PWM4 PWMLO LOWDR GND VCC BOOT HIGHDR SENSE NODE MCP14700 PWMHI PHASE PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SENSE NODE VREF dsPIC DS22201A-page 2 (c) 2009 Microchip Technology Inc. MCP14700 Functional Block Diagram VCC BOOT PWMHI Input Circuitry Level Shift HIGHDR PWMLO PHASE Logic VCC LOWDR GND VCC Protection Circuitry GND (c) 2009 Microchip Technology Inc. DS22201A-page 3 MCP14700 NOTES: DS22201A-page 4 (c) 2009 Microchip Technology Inc. MCP14700 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VCC........................................................ -0.3V to +7.0V VBOOT.................................................. -0.3V to +36.0V VPHASE ............................ VBOOT - 7V to VBOOT + 0.3V VPWM .............................................-0.3V to VCC + 0.3V VHIGHDR ......................VPHASE - 0.3V to VBOOT + 0.3V VLOWDR .........................................-0.3V to VCC + 0.3V ESD Protection on all Pins .........................2 kV (HBM) ....................................................................400V (MM) DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VCC = 5.0V, TJ = -40C to +125C Parameters VCC Supply Requirements VCC Operating Range Bias Supply Voltage UVLO (Rising VCC) UVLO Hysteresis PWM Input Requirements PWM Input Current PWM Input Current PWMLO and PWMHI Rising Threshold PWMLO and PWMHI Falling Threshold PWM Input Hysteresis Output Requirements High Output Voltage (HIGHDR and LOWDR) Low Output Voltage (HIGHDR and LOWDR) High Drive Source Resistance High Drive Sink Resistance High Drive Source Current High Drive Sink Current Low Drive Source Resistance Low Drive Sink Resistance Low Drive Source Current Low Drive Sink Current Note 1: 2: VOH VOL RHI_SRC RHI_SINK IHI_SRC IHI_SINK RLO_SRC RLO_SINK ILO_SRC ILO_SINK VCC - 0.025 -- -- -- -- -- -- -- -- -- -- -- 1.0 1.0 2.0 2.0 1.0 0.5 2.0 3.5 -- 0.025 2.5 2.5 -- -- 2.5 1.0 -- -- V V A A A A VCC = 5.0V VCC = 5.0V 500 mA source current, Note 1 500 mA sink current, Note 1 Note 1 Note 1 500 mA source current, Note 1 500 mA sink current, Note 1 Note 1 Note 1 IPWM IPWM PWMHI_TH PWMLO_TH PWMHYS -- -- 1.40 1.10 -- 7.0 1.0 1.60 1.20 400 10 -- 1.80 1.30 -- A nA V V mV VPWM = 3.0V VPWM = 0V VCC = 5.0V VCC = 5.0V VCC = 5.0V VCC IVCC VUVLO VHYS 4.5 -- -- -- 5.0 45 3.50 500 5.5 -- 4.00 -- V A V mV PWMHI and PWMLO pin floating Sym Min Typ Max Units Conditions Parameter ensured by characterization, not production tested. See Figure 4-1 and Figure 4-2 for parameter definition. (c) 2009 Microchip Technology Inc. DS22201A-page 5 MCP14700 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VCC = 5.0V, TJ = -40C to +125C Parameters Switching Times HIGHDR Rise Time LOWDR Rise Time HIGHDR Fall Time LOWDR Fall Time HIGHDR Turn-off Propagation Delay LOWDR Turn-off Propagation Delay HIGHDR Turn-on Propagation Delay LOWDR Turn-on Propagation Delay Protection Requirements Thermal Shutdown Thermal Shutdown Hysteresis Note 1: 2: TSHDN TSHDN_HYS -- -- 147 20 -- -- C C Note 1 Note 1 tRH tRL tFH tFL tPDLH tPDLL tPDHH tPDHL -- -- -- -- 20 10 20 10 10 10 10 6.0 27 17 27 17 -- -- -- -- 36 25 36 25 ns ns ns ns ns ns ns ns CL = 3.3 nF, Note 1, Note 2 CL = 3.3 nF, Note 1, Note 2 CL = 3.3 nF, Note 1, Note 2 CL = 3.3 nF, Note 1, Note 2 No Load, Note 1, Note 2 No Load, Note 1, Note 2 No Load, Note 1, Note 2 No Load, Note 1, Note 2 Sym Min Typ Max Units Conditions Parameter ensured by characterization, not production tested. See Figure 4-1 and Figure 4-2 for parameter definition. TEMPERATURE CHARACTERISTICS Unless otherwise noted, all parameters apply with VCC = 5.0V Parameter Temperature Ranges Maximum Junction Temperature Storage Temperature Specified Temperature Range Package Thermal Resistances Thermal Resistance, 8L-3x3 DFN Thermal Resistance, 8L-SOIC JA JC JA JC -- -- -- -- 64 12 163 42 -- -- -- -- C/W C/W C/W C/W Typical Four-layer board with vias to ground plane TJ TA TA -- -65 -40 -- -- -- +150 +150 +125 C C C Sym Min Typ Max Units Comments DS22201A-page 6 (c) 2009 Microchip Technology Inc. MCP14700 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C with VCC = 5.0V. 25 20 Rise Time (ns) Fall Time (ns) 15 tRL 16 14 12 10 8 6 4 2 tFL tFH 10 5 0 0 1500 3000 tRH 0 4500 6000 7500 0 1500 3000 4500 6000 7500 Capacitive Load (pF) Capacitive Load (pF) FIGURE 2-1: Load. 14 13 12 Time (ns) 11 10 9 8 7 6 -40 -25 -10 5 CLOAD = 3,300 pF Rise Time vs. Capacitive FIGURE 2-4: Load. 14 13 Fall Time vs. Capacitive CLOAD = 3,300 pF tRL tFH 12 Time (ns) 11 10 9 8 7 6 5 tRH t FL 20 35 50 65 80 95 110 125 Temperature (oC) -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) FIGURE 2-2: vs. Temperature. 36 Propagation Delay (ns) HIGHDR Rise and Fall Time FIGURE 2-5: vs. Temperature. 24 Propagation Delay (ns) LOWDR Rise and Fall Time 34 32 30 28 26 24 22 20 CLOAD = 3,300 pF tPDLH CLOAD = 3,300 pF 22 20 18 16 14 12 10 -40 -25 -10 5 t PDHL tPDHH tPDLL -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( C) o 20 35 50 65 80 95 110 125 Temperature (oC) FIGURE 2-3: vs. Temperature. HIGHDR Propagation Delay FIGURE 2-6: vs. Temperature. LOWDR Propagation Delay (c) 2009 Microchip Technology Inc. DS22201A-page 7 MCP14700 Note: Unless otherwise indicated, TA = +25C with VCC = 5.0V. 70 CLOAD = 3,300 pF 48 Supply Current (A) 47 46 45 44 43 42 41 40 PWM = 0 PWM = 1 CLOAD = 3,300 pF Supply Current (mA) 60 50 40 30 20 10 0 100 1000 Frequency (kHz) 10000 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) FIGURE 2-7: Frequency. Supply Current vs. FIGURE 2-8: Temperature. Supply Current vs. DS22201A-page 8 (c) 2009 Microchip Technology Inc. MCP14700 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE Symbol 3x3 DFN 1 2 3 4 5 6 7 8 9 SOIC 1 2 3 4 5 6 7 8 -- PHASE PWMHI PWMLO GND LOWDR VCC BOOT HIGHDR EP Switch Node High-Side PWM Control Input Signal Low-Side PWM Control Input Signal Ground Low-side Gate Drive Supply Input Voltage Floating Bootstrap Supply High-Side Gate Drive Exposed Metal Pad Description The descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP14700 3.1 Switch Node (PHASE) 3.6 Supply Input Voltage (VCC) The PHASE pin provides a return path for the high-side gate driver. The source of the high-side and the drain of the low-side power MOSFETs are connected to this pin. The VCC pin provides bias to the MCP14700 device. A bypass capacitor is to be placed between this pin and the GND pin. This capacitor should be placed as close to the MCP14700 as possible. 3.2 High-Side PWM Control Input Signal (PWMHI) 3.7 Floating Bootstrap Supply (BOOT) The PWM input signal to control the high-side power MOSFET is applied to the PWMHI pin. A logic high on the PWMHI pin causes the HIGHDR pin to also transition high. The BOOT pin is the floating bootstrap supply pin for the high-side gate drive. A capacitor is connected between this pin and the PHASE pin to provide the necessary charge to turn on the high-side power MOSFET. 3.3 Low-Side PWM Control Input Signal (PWMLO) 3.8 High-Side Gate Drive (HIGHDR) The PWM input signal to control the low-side power MOSFET is applied to the PWMLO pin. A logic high on the PWMLO pin causes the LOWDR pin to also transition high. The HIGHDR pin provides the gate drive signal to control the high-side power MOSFET. The gate of the high-side power MOSFET is connected to this pin. 3.9 Exposed Metal Pad (EP) 3.4 Ground (GND) The GND pin provides ground for the MCP14700 circuitry. It should have a low-impedance connection to the bias supply source return. High peak currents will flow out the GND pin when the low-side power MOSFET is being turned off. The exposed metal pad of the DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a printed circuit board to aid in heat removal from the package. 3.5 Low-side Gate Drive (LOWDR) The LOWDR pin provides the gate drive signal to control the low-side power MOSFET. The gate of the low-side power MOSFET is connected to this pin. (c) 2009 Microchip Technology Inc. DS22201A-page 9 MCP14700 NOTES: DS22201A-page 10 (c) 2009 Microchip Technology Inc. MCP14700 4.0 4.1 DETAILED DESCRIPTION Device Overview The MCP14700 is a synchronous MOSFET driver with dual independent PWM inputs capable of controlling both a ground referenced and floating N-Channel MOSFET. The PWM input threshold levels are truly 3.0V logic tolerant and have 400 mV of typical hystereses making the MCP14700 ideal for use with low voltage controllers. The MCP14700 is capable of suppling 2A (typical) peak current to the floating high-side MOSFET that is connected to the HIGHDR. With the exception of a capacitor, all of the circuitry needed to drive this high-side N-channel MOSFET is internal to the MCP14700. A blocking device is placed between the VCC and BOOT pins that allows the bootstrap capacitor to be charged to VCC when the low-side power MOSFET is conducting. Refer to the application section, Section 5.1 "Bootstrap Capacitor Select", for information on determining the proper size of the bootstrap capacitor. The HIGHDR is also capable of sinking 2A (typical) peak current. The LOWDR is capable of sourcing 2A (typical) peak current and sinking 3.5A (typical) peak current. This helps ensure that the low-side MOSFET stays turned off during the high dv/dt of the PHASE node. When designing with the MCP14700 in applications where cross conduction of the external MOSFETs is not desired, care must be taken to ensure the PWM inputs have the proper timing. There is no internal cross conduction protection in the MCP14700. 4.3 Under Voltage Lockout (UVLO) The UVLO feature of the MCP14700 does not allow the HIGHDR or LOWDR output to function when the input voltage, VCC, is below the UVLO threshold regardless of the state of the PWMHI and PWMLO pins. Once VCC reaches the UVLO threshold, the HIGHDR and LOWDR outputs will respond to the state of the PWMHI or PWMLO pins. There is a 500 mV hystereses on the UVLO threshold. 4.4 Overtemperature Protection The MCP14700 is protected from an overtemperature condition by an internal thermal shutdown feature. When the internal temperature of the MCP14700 reaches 147C typically, the HIGHDR and LOWDR outputs will transition to a low state regardless of the state of the PWMHI or PWMLO pins. Once the internal temperature is reduced by 20C typically, the MCP14700 will automatically respond to the states of the PWMHI and PWMLO pins. 4.2 PWM Inputs 4.5 Timing Diagram A logic high on either PWM pin causes the corresponding output drive signal to be high. See Figure 4-1 and Figure 4-2 for a graphical representation of the MCP14700 operation. Internally the PWM pins are pulled to ground to ensure there is no drive signal to the external MOSFETs if the pins are left floating. For reliable operation, it is recommended that the rising and falling slew rate of the PWM signal be faster than 1V/50 ns. The PWM signal applied to the MCP14700 is supplied by a controller IC. The timing diagram in Figure 4-1 graphically depicts the PWM signal and the output signals of the MCP14700. PWMLO tPDHL tPDLL LOWDR tRL tFL FIGURE 4-1: MCP14700 LOWDR Timing Diagram. (c) 2009 Microchip Technology Inc. DS22201A-page 11 MCP14700 PWMHI tPDHH tPDLH HIGHDR tRH tFH FIGURE 4-2: MCP14700 HIGHDR Timing Diagram. DS22201A-page 12 (c) 2009 Microchip Technology Inc. MCP14700 5.0 5.1 APPLICATION INFORMATION Bootstrap Capacitor Select 5.3 Power Dissipation The selection of the bootstrap capacitor is based upon the total gate charge of the high-side power MOSFET and the allowable droop in gate drive voltage while the high-side power MOSFET is conducting. The power dissipated in the MCP14700 consists of the power loss associated with the quiescent power and the gate charge power. The quiescent power loss can be calculated by the following equation and is typically negligible compared to the gate drive power loss. EQUATION 5-1: Q GATE C BOOT ---------------------------V DROOP Where: CBOOT QGATE VDROO For example: QGATE = 30 nC VDROOP = 200 mV CBOOT 0.15 uF A low ESR ceramic capacitor is recommend with a maximum voltage rating that exceeds the maximum input voltage, VCC, plus the maximum supply voltage, VSUPPLY. It is also recommended that the capacitance of CBOOT does not exceed 1.2 uF. = = = Bootstrap capacitor value Total gate charge of the high-side MOSFET Allowable gate drive voltage droop EQUATION 5-2: P Q = I VCC x V CC Where: PQ = Quiescent power loss IVCC = No Load Bias Current VCC = Bias Voltage The main power loss occurs from the gate charge power loss. This power loss can be defined in terms of both the high-side and low-side power MOSFETs. EQUATION 5-3: P GATE = P HIGHDR + P LOWDR P HIGHDR = V CC x Q HIGH x F SW P LOWDR = V CC x Q LOW x F SW Where: PGATE = PHIGHDR = PLOWDR VCC = = Total Gate Charge Power Loss High-Side Gate Charge Power Loss Low-Side Gate Charge Power Loss Bias Supply Voltage High-Side MOSFET Total Gate Charge Low-Side MOSFET Total GAte Charge Switching Frequency 5.2 Decoupling Capacitor Proper decoupling of the MCP14700 is highly recommended to help ensure reliable operation. This decoupling capacitor should be placed as close to the MCP14700 as possible. The large currents required to quickly charge the capacitive loads are provided by this capacitor. A low ESR ceramic capacitor is recommended. QHIGH = QLOW = FSW = (c) 2009 Microchip Technology Inc. DS22201A-page 13 MCP14700 5.4 PCB Layout Proper PCB layout is important in a high current, fast switching circuit to provide proper device operation. Improper component placement may cause errant switching, excessive voltage ringing, or circuit latch-up. There are two important states of the MCP14700 outputs, high and low. Figure 5-1 depicts the current flow paths when the outputs of the MCP14700 are high and the power MOSFETs are turned on. The charge needed to turn on the low-side power MOSFET comes from the decoupling capacitor CVCC. The current flows from this capacitor through the internal LOWDR circuitry, into the gate of the low-side power MOSFET, out the source, into the ground plane, and back to CVCC. To reduce any excess voltage ringing or spiking, the inductance and area of this current loop must be minimized. Figure 5-2 depicts the current flow paths when the outputs of the MCP14700 are low and the power MOSFETs are turned off. These current paths should also have low inductance and a small loop area to minimize the voltage ringing and spiking. CBOOT MCP14700 PWMHI PWMLO VCC VSUPPLY CVCC CBOOT MCP14700 PWMHI PWMLO VCC VSUPPLY FIGURE 5-2: Turn Off Current Paths. The following recommendations should be followed for optimal circuit performance: - The components that construct the high current paths previously mentioned should be placed close the MCP14700 device. The traces used to construct these current loops should be wide and short to keep the inductance and impedance low. - A ground plane should be used to keep both the parasitic inductance and impedance minimized. The MCP14700 device is capable of sourcing and sinking high peaks current and any extra parasitic inductance or impedance will result in non-optimal performance. CVCC FIGURE 5-1: Turn On Current Paths. The charge needed to turn on the high-side power MOSFET comes from the bootstrap capacitor CBOOT. Current flows from CBOOT through the internal HIGHDR circuitry, into the gate of the high-side power MOSFET, out the source and back to CBOOT. The printed circuit board traces that construct this current loop need to have a small area and low inductance. To control the inductance, short and wide traces must be used. DS22201A-page 14 (c) 2009 Microchip Technology Inc. MCP14700 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead DFN (3x3) Device MCP14700 Code DABR Example: XXXX YYWW NNN Note: Applies to 8-Lead 3x3 DFN DABR 0933 256 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN 14700E SN e3 0933 256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. 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DS22201A-page 17 MCP14700 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D e N E E1 NOTE 1 1 2 3 b h c h A A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS22201A-page 18 (c) 2009 Microchip Technology Inc. MCP14700 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2009 Microchip Technology Inc. DS22201A-page 19 MCP14700 NOTES: DS22201A-page 20 (c) 2009 Microchip Technology Inc. MCP14700 APPENDIX A: REVISION HISTORY Revision A (September 2009) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS22201A-page 21 MCP14700 NOTES: DS22201A-page 22 (c) 2009 Microchip Technology Inc. MCP14700 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device MCP14700: MCP14700T: Dual Input Synchronous MOSFET Driver Dual Input Synchronous MOSFET Driver Tape and Reel (DFN and SOIC) Extended Temperature, 8LD DFN package. MCP14700T-E/MF: Tape and Reel, Extended Temperature, 8LD DFN package. Extended Temperature, 8LD SOIC package. MCP14700T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP14700-E/SN: MCP14700-E/MF: a) b) Temperature Range E = -40C to +125C (Extended) Package MF = Plastic Dual Flat, No Lead (3x3 DFN), 8-lead SN = Plastic Small Outline, (3.90 mm), 8-lead (c) 2009 Microchip Technology Inc. DS22201A-page 23 MCP14700 NOTES: DS22201A-page 24 (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. 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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. 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